Breaking the AI Power Wall: A Conversation with Powerlattice

August 11, 2026

Conventional power-delivery systems were designed decades ago for chips consuming a few hundred watts. But the AI industry has spent years developing processors capable of performing more computation and the most advanced AI processors are now moving toward power requirements measured in thousands of watts, creating new challenges around efficiency, heat, response time, and the physical space required for power components.

Powerlattice is addressing that problem at the point of load, the final stage before electricity reaches the system-on-chip. Its power-delivery chiplet moves voltage regulation from the circuit board directly into the processor package, placing power within millimeters of where computation occurs.

In this conversation, Powerlattice co-founder Sujith Dermal explains why power delivery has become a critical bottleneck for AI infrastructure, the technical breakthroughs behind the company's architecture, and what it takes to move a new semiconductor platform from first principles to production.

‍

Conventional power-delivery systems were designed decades ago for chips consuming a few hundred watts. But the AI industry has spent years developing processors capable of performing more computation and the most advanced AI processors are now moving toward power requirements measured in thousands of watts, creating new challenges around efficiency, heat, response time, and the physical space required for power components.

Powerlattice is addressing that problem at the point of load, the final stage before electricity reaches the system-on-chip. Its power-delivery chiplet moves voltage regulation from the circuit board directly into the processor package, placing power within millimeters of where computation occurs.

In this conversation, Powerlattice co-founder Sujith Dermal explains why power delivery has become a critical bottleneck for AI infrastructure, the technical breakthroughs behind the company's architecture, and what it takes to move a new semiconductor platform from first principles to production.

‍

For readers hearing about Powerlattice for the first time, what is the company building?

Powerlattice's goal is to break the power wall for AI compute by reimagining point-of-load power delivery, the final stage where power is delivered to the processor.

AI processors are moving toward power requirements of 3,000 or even 4,000 watts. Existing power-delivery technologies were never designed for that level of demand. We are introducing a fundamentally different architecture that brings power much closer to where the computation actually occurs.

‍

Why has power delivery become such an important constraint now?

The underlying technologies used in conventional power delivery are several decades old. They were developed to supply processors consuming 100, 200, or 300 watts, and the industry has continued adopting those same approaches even though processor power needs have increased way beyond those power supplies could initially support.

That legacy architecture is now reaching its limits. Traditional components sit far from the processor, are bulky, and very slow. The response time is inadequate to the rapid changes in current demand by latest AI workloads.

Compute performance has advanced much faster than the infrastructure delivering power to it. Historically, power-supply design was largely treated as a separate discipline from processor design. Today, that boundary needs to be changed as power is becoming the primary factor determining processor performance and overall compute efficiency.

‍

What is the core breakthrough behind Powerlattice's technology?

We have combined the multiple technologies required for point-of-load power delivery into a single monolithic chiplet. That includes the power transistors, on-chip inductors, scalable and configurable circuit architecture, control circuitries, and advanced IC packaging to deliver a stable voltage to the power hungry compute SoCs.

That level of integration gave us the speed and density to form a chiplet which enables the power-delivery system into the processor package rather than on the PCB.

Conventional point-of-load power delivery is the "last inches" of the system. Powerlattice turns those last inches into the last millimeters. The increased density and speed significantly reduces the overall system power consumption and helps achieve a step function gain in performance/watt for high performance compute.

‍

A number of companies are pursuing new approaches to AI power. Where does Powerlattice differentiate?

Our primary differentiation is the degree of integration we can achieve and the performance/watt gain.

Our proprietary on-chip inductors along with the circuit and system architecture, allows our chiplet to be integrated directly into the processor package. Powerlattice is uniquely positioned to have multiple disciplines under the same umbrella to achieve this level of integration compared to any incumbents out there.

The next biggest differentiator is programmability. Powerlattice has developed a standard architecture that can be configured and programmed for different SoCs. That makes the platform scalable across existing and future processors. We can adapt to the customer's requirements without being dependent on the SoC design of any single GPU, CPU, or accelerators. I.e, the customer only has to redesign the package substrate and no change in the SoC design is needed.

‍

Processor companies introduce new products every year. How do you keep up?

The programmability feature of our chiplet is an important part of the answer. Because the chiplet can be configured for different processor power requirements, we are well suited for multiple generations of SoCs.

In addition to the programmability, we're also working on our road map products which will offer increasingly higher performance for the future power demands to scale the AI compute.

‍

Conventional point-of-load power delivery is the "last inches" of the system. Powerlattice turns those last inches into the last millimeters.

‍

Can you share some of the progress Powerlattice has made since emerging from stealth last fall?

We moved from the start of the design to shipping initial customer samples in approximately 13-14 months, which is exceptionally fast for this space.

Since coming out of stealth, we have seen a significant increase in customer interests. Our focus now is supporting customer evaluations, complete functional and reliability qualification testings both internally and also at customers, and increase the supply chain capacity for high volume production of our chiplets.

‍

How did the founding team come together, and why did you decide to start the company?

My co-founders Peng Zou, Gang Ren, and I worked together previously at NUVIA.

We were interested in solving the emerging power wall in servers and AI infrastructure. When we had the opportunity to start something independently, we decided to focus entirely on that challenge.

For roughly 12 months, the three of us incubated the idea. We focused on developing the architecture fundamentals of a scalable system, a single design that could support multiple customers, and understanding required manufacturing and supply-chain capabilities before beginning execution.

The preparation before tape-out was essential to the speed we achieved afterward.

‍

Semiconductor startups are raising increasingly large amounts of capital. How are you approaching scaling the company?

We have tried to be measured and thoughtful. Capital is important, but so is deploying it against the right stage of the company's development.

A new CPU or GPU company may require a very large team and an enormous amount of capital before it can produce its first silicon. We on the other hand are developing an analog and mixed-signal power chiplet, which allows us to operate with a smaller and more focused R&D organization with a smaller sized capital compared to other semiconductor startups (xPU, Packaged Optics, Quantum)

That said, the value of the solution can still be substantial. Power delivery affects every high-performance processor, and even incremental efficiency gains translate into significant system-level savings at data-center scale.

Our approach has been to build a highly experienced, cross-disciplinary team and establish a strong first layer of technical leadership before expanding the organization. Now that we have working silicon, the focus is shifting to customer support, qualification, manufacturing, and the transition to volume production.

What kind of support matters most from investors at this stage?

Supply-chain development is one of the most important areas. Customers need confidence that we can support high-volume production. That requires us to establish a diversified, multisource supply chain that demonstrates the necessary resilience.

We also value help with scaling the company and navigating commercial relationships. Technical validation is only one part of winning a major semiconductor customer. There are complex negotiations, integration cycles, manufacturing decisions, and long-term commitments involved.

This is precisely why we chose investors with deep semiconductor and operating experience, because we needed more than capital. Celesta and Playground Global understand hardware, the timelines required to bring it to market, and the infrastructure a company needs to become a durable supplier.

The opportunity in AI power delivery is large and growing. Our job now is to support our customers, prove the technology through qualification and deployment, and build the organization and supply chain capable of meeting that demand.

‍

Recent News