The AI Revolution Relies on Advanced Packaging

• Advanced packaging makes up the literal building blocks for AI compute and memory
• The market for these structures is projected to grow significantly in the future

We discover new artificial intelligence (AI) use cases daily. AI answers our questions, writes emails, creates and edits videos, summarizes transcripts, codes, and more. AI chips-specifically designed to handle the unique computational demands of processing large language models (LLMs)-enable these advanced offerings.

Because AI requires massive computing power, chip designers like Intel, AMD, and NVIDIA are trying to keep up, and are now joined by other companies like Google, Meta, Amazon, and Tesla to design and create advanced AI chips.

Where are these AI chip manufacturers making the most significant leaps forward? The answer is advanced packaging.

Packaging Benefits: Enhancing AI Performance and Efficiency

One way to think of advanced packaging-the joining of multiple chips (or chiplets) and components into a single chip-is in terms of building blocks. This building block approach allows us to push the very limits of Moore's Law because chip components are no longer limited to horizontal layouts.

Graphics processing units (GPUs) and memory chips (individual chips collected into a larger chip) can be configured to allow data and power to move quickly and efficiently, relying on different technologies and designs to connect chiplets in a way most suited to the chip's purpose in a device.

The key drivers and benefits of AI packaging include:

• Optimized performance: By packaging memory and processors together, data is transferred much more efficiently, providing the fast, powerful capabilities needed for AI applications.
• Power: Devices built using advanced packaging are more energy efficient by optimizing the layout and interconnection of components.
• Form factor: By stacking components vertically, advanced packaging helps manufacturers meet the ever-increasing demand for smaller, more portable devices.
• Cost: By separating chips into chiplets, we can use the most cost-optimal manufacturing technology for each chiplet instead of subjecting everything to the latest, expensive single advanced node fabrication process. This can provide cost savings.

CoWoS Packaging: NVIDIA's H100 AI Chip Example

NVIDIA's H100 AI chip is one example of chip on wafer on substrate (CoWoS) packaging. This chip has one powerful GPU and six high bandwidth memory (HBM) stacks, each formed by vertically connecting eight to 12 HBM memory chips. The GPU and HBM stacks-or chiplets-are manufactured separately, joined on a silicon wafer, then cut into individually packaged chips. Each of these packaged chips is then adhered to a high-density interconnect (HDI) board (the substrate). Hence the term chip on wafer on substrate.

The HBM dies (as chips are often called) are collected into a single stacked tower, and the GPU sits between the stacks on the silicon wafer (referred to as aninterposer layer). In this configuration, called 2.5D, the GPU sits on a 2D horizontal plane, and the HBMs are stacked in a 3D configuration.

The evolution of high bandwidth memory (HBM) stacks, formed by vertically connecting increasing layers of memory chips.

Another example of a CoWoS design uses silicon bridges embedded within an organic interposer. Using organic material (versus silicon or glass) for the interposer makes the layer more flexible, lightweight, and inexpensive. By embedding silicon within organic interposers to serve as bridges between HBM and GPU dies, chip manufacturers can avoid the expense of an all-silicon interposer and increase package sizes beyond the reticle limit to produce larger, more complex, and higher-performance devices.

Organic interposers (right) are more flexible, lighter, and cheaper than those made from silicon or glass.

Connection Types in Advanced Packaging

Four of the connections most used in the building-block approach are:

• Bumps: These are protruding conductive structures that connect dies to packaging or other components. Bumps provide the electrical connections necessary for chips to function.
• Redistribution layer (RDL): This layer connects one part of a semiconductor package to another through very fine copper lines on a horizontal plane, allowing the transfer of data, power, and ground signals.
• Through-silicon vias (TSV): These are metal connections that run through tiny vertical holes running through a silicon layer, allowing chiplets on top of the layer to connect to other chiplets.
• Hybrid bonding interconnect (HBI): This strong adhesive bond between chip layers provides structural support, enables data flow between chips, and dissipates heat.

Connections within a chip, referred to asback-end-of-line (BEOL), are the intricate network of wires that connect components within a chip, distributing power and ground signals. The BEOL is, in essence, the infrastructure that allows the building blocks to work together in a way that is faster, smaller, and more efficient.

Front-End Processing in Advanced Packaging

The concept of advanced packaging, considered a back-end process (like traditional integrated circuit packaging), has been around for decades. Advanced packaging today relies on the front-end processes performed in fabs.

For example, in the U-bump/RDL packaging process, a thin film barrier is first deposited on an incoming wafer through physical vapor deposition (PVD). The wafer is patterned by depositing photoresist materials on the film. The wafer is then "descummed," a process that removes photoresist residue, after which material is deposited in an electroplating process. Finally, the remaining photoresist material is stripped from the wafer, and the PVD film is etched away. These processes are also used to create the chiplets within the package.

TSV packaging is much more complex: The pattern mask is created on the wafer, which is then etched to selectively remove the film and define the chip's features. After etching, cleaning removes the photoresist residue and any remaining particles deposited on the wafer during etching. Then PVD and electroplating deposit a film barrier on the wafer to create the TSV connections. The chip is then polished to remove excess material deposited during electroplating, after which it is attached to a carrier and flipped upside down. Finally, the exposed side of the wafer is ground, etched to reveal the TSVs, and coated with a protective film in a process called passivation.

Lam has been in the advanced packaging market for more than 20 years. Our tools support the creation of bumps, pillars, RDL, TSVs, TDVs, TGVs, and hybrid bonding.

• TSV: A vertical connection that passes through the entire thickness of a silicon wafer to connect different layers of a chip, enabling 3D integration.
• Through dielectric via (TDV): A vertical connection that passes through a reconstituted chip to connect layers within that chip, enabling 3D integration.
• Through glass via (TGV): A vertical connection that passes through a glass interposer layer to connect multiple chips together in a 3D stack.

TSV Formation: Key to 3D Integration

For high aspect ratio (HAR) features, TSV formation demands HAR etch, conformal deposition, and consistent TSV fill, all enabled by Lam tools.

• Syndion® products feature an excellent etch rate and produce uniform holes with minimal roughness of their side walls, resulting in fewer chip defects.
• Striker® ALD deposition products provide excellent conformality, electric reliability, and low shrinkage, ensuring consistent flow of data and power through a chip.
• The SABRE® 3D electrofill product family can produce void-free fill for a wide range of TSV sizes, as well as on-wafer performance stability, resulting in a wide range of design possibilities for complex chips.

RDL Formation: Creating Connections for Advanced Packaging

Lam's technologies facilitate the redistribution layer (RDL) formation, which is key for creating the connections needed to fan out I/Os from the chip over a larger area. This technology supports increased performance and functionality in the smaller footprint provided by advanced packaging.

TurboCell HW cleaning has proved successful for RDL interposer formation, by addressing two key challenges to manufacturers:

• Fine-line RDL: Plating RDL copper lines smaller than 5x5 micrometers using standard etch processes can result in a loss of critical dimension (CD), rough sidewalls, and undercutting, all of which can degrade line quality and, in turn, reduce signal integrity. In addition, at that small size, coefficient of thermal expansion (CTE) mismatches between materials can cause the fine copper lines to warp and break. However, a proprietary technology using TurboCell HW plating processes has led to higher uniformity even on thin seed, allowing a shorter downstream seed-over-etch process. In addition, using nanotwinned (tiny, parallel structures within a material that are only a few atoms thick) copper lines are stronger and more resistant to breakage.
• Megapillars: Using the standard process to produce copper pillars larger than 150x150 micrometers, pillar height grows less precisely as the speed increases. But slowing the process results in higher costs. A grinding step is employed to planarize nonuniform pillars. Our next-generation TurboCell HW cleaning process allows a more uniform pillar, thereby saving costs through a shorter grinding step.

PLP Support: Advancements in Panel-Level Packaging

Another advancement in advanced packaging is panel-level packaging (PLP), in which integrated circuits (ICs) are assembled and packaged onto a single panel and tested together before being separated into individual packages. Lam's Kallisto® and Phoenix panel platers support PLP, with these advantages:

• Higher possible density of ICs on panels than silicon wafers, reducing the overall footprint and cost.
• Lower manufacturing costs by eliminating some steps from the packaging process, such as individual die handling and testing.

Depth Uniformity: Ensuring Consistency in Advanced Packaging

One of the biggest challenges in advanced packaging is measuring TSV hole depth to confirm uniformity across the hundreds of thousands of holes on a wafer after the TSV etch is complete. This can be accomplished by examining the cross-section of a wafer, but cross-sectioning every wafer is not feasible.

Enter Lam's Metior® family of metrology tools : By comparing the measurements of every wafer before and after fabrication, engineers can identify wafers with defects. Using this method, a significant number of wafers can be evaluated at a low cost and without the need to destroy any of the wafers (i.e., breaking wafers to measure physical dimensions).

AI Breakthroughs: The Role of Advanced Packaging

As the demand for AI applications continues to soar, advanced packaging will play a pivotal role in driving innovation and performance. Lam's commitment to providing cutting-edge equipment solutions positions the industry to meet the challenges and opportunities of the future. By enabling breakthroughs in packaging technologies, Lam is helping shape the next generation of AI chips, powering the AI revolution and unlocking its full potential.

Chee Ping Lee is managing director of advanced packaging strategic marketing at Lam Research.

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